Typical prior art multiport register files are shown in, for example, U.S. Pat. Nos. 4,535,428, issued Aug. 13, 1985 to Anatol Furman; and 4,558,433 issued Dec. 10, 1985 to Cary Bernstein. The disclosures of those patents are hereby incorporated by reference for background information.
Multiport register files normally operate from a clock signal which controls the timing of reading and writing operations with respect to the register file's memory. Typically, the clock cycle establishes specific times when data can be written into the register file and other times when data can be read from the register file. For example, during the first half of a clock cycle, data may be written into the memory; and during the second half of the clock cycle, data may be read from the memory. Therefore, in such normal operation, when data is to be passed from a particular input port to a particular output port of the multiport register file, the data must first be written into the RAM during one clock cycle and then read out from the RAM during the next (or a later) clock cycle.
Additional restrictions on read/write operation may be imposed by the internal architecture of these devices. As stated in the Bernstein and Furman patents, care must be taken in such multiport register files to protect the integrity of the stored data during read and write operations. Normally, the bitlines in a RAM cell (i.e., the conductors over which data bits are supplied for writing to or reading from the cells) are pre-charged to a level corresponding to the complementary value of the cell data. If a number of ports are turned on simultaneously to access a given cell, though, that cell may lose its data. To avoid this loss of data, larger size, more elaborate cell structures may be used or cell access can be restricted to one set of bitlines at a time, with data being reapplied to the other ports as required, outside the RAM structure itself. That is, when an address coincidence is detected among the ports (indicating that two or more ports seek access to the same data cell), only one word line is enabled, limiting access to a single port. The port is selected according to a predetermined list of priorities. Comparators then switch an appropriate multiplexer so that the highest priority bitlines are also routed to the lower priority ports. Such operation is explained in greater detail in the Furman and Bernstein patents, incorporated by reference herein.
Sometimes, though, it is desirable (and even important) to be able to pass data from an input (or write) port of a multiport register file to an output (or read) port thereof in the same cycle, instead of waiting for the usual delay of one or more cycles. This desired operation is referred to as "flow-through" of data. The multiple read inhibit scheme employed by Bernstein, Furman and others, however, imposes restrictions on the achievement of flow-through operation since they do not permit an input port and an output port simultaneously to access a single cell.
Accordingly, it is an object of the present invention to provide an improved multiport register file.
It is a further object of the present invention to provide a multiport register file supporting flow-through of data, whereby data presented at an input port of the register file during a given clock cycle can be passed to an output port of said file in the same cycle (and, preferably, in the same half cycle).
Yet another object of the invention is to provide a multiport register file supporting flow-through of data together with inhibition of multiple read operation.